integrated circuit systems, inc. general description features ics9112-17 0051k?11/02/04 block diagram low skew output buffer pin configuration zero input - output delay frequency range 25 - 133 mhz (3.3v) high loop filter bandwidth ideal for spread spectrum applications. less than 200 ps cycle to cycle jitter skew controlled outputs skew less than 250 ps between outputs available in 16 pin, 150 mil ssop & soic package the ics9112-17 is a high performance, low skew, low jitter zero delay buffer. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the ref input with the clkout signal. it is designed to distribute high speed clocks in pc systems operating at speeds from 25 to 133 mhz. ics9112-17 is a zero delay buffer that provides synchronization between the input and output. the synchronization is established via clkout feed back to the input of the pll. since the skew between the input and output is less than +/- 350 ps, the part acts as a zero delay buffer. the ics9112-17 has two banks of four outputs controlled by two address lines. depending on the selected address line, bank b or both banks can be put in a tri-state mode. in this mode, the pll is still running and only the output buffers are put in a high impedance mode. the test mode shuts off the pll and connects the input directly to the output buffers (see table below for functionality). the ics9112-17 comes in a sixteen pin 150 mil soic or 16 pin ssop package. in the absence of ref input, will be in the power down mode. in this mode, the pll is turned off and the output buffers are pulled low. power down mode provides the lowest power consumption for a standby condition. 2 s f1 s f a k l c ) 4 , 1 ( b k l c ) 4 , 1 ( t u o k l c t u p t u o e c r u o s l l p n w o d t u h s 00 e t a t s i r te t a t s i r tn e v i r dl l pn 01 n e v i r de t a t s i r tn e v i r dl l pn 10 l l p s s a p y b e d o m l l p s s a p y b e d o m l l p s s a p y b e d o m f e ry 11 n e v i r dn e v i r dn e v i r dl l pn functionality 16 pin ssop & soic
2 ics9112-17 0051k?11/02/04 pin descriptions notes: 1. guaranteed by design and characterization. not subject to 100% test. 2. weak pull-down 3. weak pull-down on all outputs 4. weak pull-ups on these inputs r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 1f e r 2 n i. y c n e u q e r f e c n e r e f e r t u p n i 21 a k l c 3 t u oa k n a b , t u p t u o k c o l c d e r e f f u b 32 a k l c 3 t u oa k n a b , t u p t u o k c o l c d e r e f f u b 3 1 , 4d d vr w p) v 3 . 3 ( y l p p u s r e w o p 2 1 , 5d n gr w pd n u o r g 61 b k l c 3 t u ob k n a b . t u p t u o k c o l c d e r e f f u b 72 b k l c 3 t u ob k n a b . t u p t u o k c o l c d e r e f f u b 82 s f 4 n i2 t i b , t u p n i t c e l e s 91 s f 4 n i1 t i b , t u p n i t c e l e s 0 13 b k l c 3 t u ob k n a b . t u p t u o k c o l c d e r e f f u b 1 14 b k l c 3 t u ob k n a b . t u p t u o k c o l c d e r e f f u b 4 13 a k l c 3 t u oa k n a b , t u p t u o k c o l c d e r e f f u b 5 14 a k l c 3 t u oa k n a b , t u p t u o k c o l c d e r e f f u b 6 1t u o k l c 3 t u on i p s i h t n o k c a b d e e f l a n r e t n i , t u p t u o k c o l c d e r e f f u b
3 ics9112-17 0051k?11/02/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input & supply t a = 0 - 70c; supply voltage v dd = 5.0 v +/-10% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2.0 2.5 vdd +0.5 v input low voltage v il gnd -0.5 0.8 v input high current i ih v in = v dd 0.1 100 ua input low current i il v in = 0 v; 19 50 ua operating current i dd1 c l = 0 pf; f in @ 66m 45 65 ma input frequency f i 1 v dd = 3.3 v; all outputs loaded 25 133 mhz input capacitance c in 1 logic inputs 5 pf 1 guaranteed by design, not 100% tested in production. electrical characteristics - input & supply t a = 0 - 70c; supply voltage v dd = 3.3 v +/-10% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2.0 2.0 v dd +0. 3 v input low voltage v il gnd-0.3 0.8 v input high current i ih v in = v dd 0.1 100 ua input low current i il v in = 0 v; 19 50 ua operating current i dd1 c l = 0 pf; f in @ 66m 30 45 ma input frequency f i 1 v dd = 3.3 v; all outputs loaded 25 133 mhz input capacitance c in 1 logic inputs 5.0 pf 1 guarenteed by design, not 100% tested in production.
4 ics9112-17 0051k?11/02/04 electrical characteristics - output t a = 0 - 70c; v dd = v ddl = 3.3 v +/-10%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp v o = v d d *(0.5) 10 24 ? output impedance r dsn v o = v d d *(0.5) 10 24 ? output high voltage v oh i oh = -8 ma 2.4 2.9 3.3 v output low voltage v ol i ol = 8 ma 0.25 0.4 v rise time 1 t r v ol = 0.8 v, v oh = 2.0 v 1.2 2.0 ns fall time 1 t f v oh = 2.0 v, v ol = 0.8 v 1.2 2.0 ns pll lock time1 tlock stable power supply, valid clock presented on ref pin 1.0 ms d t v t = 1.4v;cl=30pf 40 50 60 % d t v t = vdd/2; fout <66.6mhz 45 50 55 % tcyc-cyc at 66mhz , loaded outputs 250 ps tcyc-cyc >66mhz , loaded outputs 200 ps absolute jitter 1 tjabs 10000 cycles; cl= 30pf -100 70 100 ps jitter; 1-sigma 1 tj1s 10000 cycles; cl= 30pf 14 30 ps skew 1 t sk v t = 1.4 v (window) output to output 250 ps d evice to device ske w 1 tdsk-tdsk measured at vdd/2 on the clkout pins of devices 0700ps delay input-output 1 d r1 v t = 1.4 v 0700ps 1 guaranteed by design, not 100% tested in production. cycle to cycle jitter 1 duty cycle 1 electrical characteristics - output t a = 0 - 70c; v dd = v ddl = 5.0 v +/-10%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp v o = v dd *(0.5) 10 24 ? output impedance r dsn v o = v dd *(0.5) 10 24 ? output high voltage v oh i oh = -8 ma 2.4 2.9 5.0 v output low voltage v ol i ol = 8 ma 0.25 0.4 v rise time 1 t r v ol = 0.8 v, v oh = 2.0 v 0.8 1.5 ns fall time 1 t f v oh = 2.0 v, v ol = 0.8 v 1.0 1.5 ns pll lock time 1 tlock stable power supply, valid clock presented on ref pin 1.0 ms duty cycle 1 d t v t = 1.4v;cl=30pf 40 50 60 % tcyc-cyc at 66mhz , loaded outputs 250 ps tcyc-cyc >66mhz , loaded outputs 200 ps absolute jitter 1 tjabs 10000 cycles; cl= 30pf -100 60 100 ps jitter; 1-si g ma 1 tj1s 10000 c y cles; cl=30pf 14 30 ps skew 1 t sk v t = 1.4 v (window) output to output 250 ps device to device skew 1 tdsk-tdsk measured at vdd/2 on the clkout pins of devices 0 700 ps delay input-output 1 d r1 v t = 1.4 v 0 700 ps 1 guaranteed by design, not 100% tested in production. cycle to cycle jitter 1
5 ics9112-17 0051k?11/02/04 output to output skew the skew between clkout and the clka/b outputs is not dynamically adjusted by the pll. since clkout is one of the inputs to the pll, zero phase difference is maintained from ref to clkout. if all outputs are equally loaded, zero phase difference will maintained from ref to all outputs. if applications requiring zero output-output skew, all the outputs must equally loaded. if the clka/b outputs are less loaded than clkout, clka/b outputs will lead it; and if the clka/b is more loaded than clkout, clka/b will lag the clkout. since the clkout and the clka/b outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. ref input and all outputs loaded equally ref input and clka/b outputs loaded equally, with clkout loaded more . ref input and clka/b outputs loaded equally, with clkout loaded less . timing diagrams with different loading configurations
6 ics9112-17 0051k?11/02/04 application suggestion: ics9112-17 is a mixed analog/digital product. the analog portion of the pll is very sensitive to any random noise generated by charging or discharging of internal or external capacitor on the power supply pins. this type of noise will cause excess jitter to the outputs of ics9112-17. below is a recommended lay out to alleviate any addition noise. for additional information on ft. layout, please refer to our an07. the 0.1 uf capacitors should be connected as close as possible to power pins (4 & 13). an isolated power plane with a 2.2 uf capacitor to ground will enhance the power line stability. 33 ? 33 ? 33 ? 33 ? 10k ? 0.1f vdd gnd 33 ? 33 ? 33 ? 33 ? 33 ? 10k ? 0.1f vdd gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ref clka1 clka2 vdd gnd clkb1 clkb2 fs2 clkout clka4 clka3 vdd gnd clkb4 clkb3 fs1
7 ics9112-17 0051k?11/02/04 ordering information 9112 y f-17lf-t min max min max a 1.35 1.75 .053 .069 a1 0.10 0.25 .004 .010 a2 -- 1.50 -- .059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 d e 5.80 6.20 .228 .244 e1 3.80 4.00 .150 .157 e l 0.40 1.27 .016 .050 n 0 8 0 8 zd zd zd min max (ref) min max (ref) 16 4.80 5.00 0.23 .189 .197 .009 10-0032 reference doc.: jedec publication 95, mo-137 see variations 0.635 basic variations n see variations d (inch) see variations d mm. see variations 150 mil ssop (qsop) c ommon dimension s see variations 0.025 basic see variations symbol in millimeters common dimensions in inches example: designation for tape and reel packaging lead option (optional) lf = lead free ln = lead free annealed pattern number (2 or 3 digit number for parts with rom code patterns) package type f = ssop revision designator (will not correlate with datasheet revision) device type p xxxx y f ppp lx- t
8 ics9112-17 0051k?11/02/04 ordering information 9112 y m-17lf-t seating plane seating plane a1 b a e .10 (.004) .10 (.004) h x 45 h x 45 l c index area index area 12 1 2 n d e h min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d e 3.80 4.00 .1497 .1574 e h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 n 0 8 0 8 variations min max min max 16 9.80 10.00 .3859 .3937 10-0030 0.050 basic symbol in millimeters in inches common dimensions common dimensions reference doc.: jedec p ublication 95, m s-012 150 mil (narrow body) soic see variations see variations n d mm. d (inch) see variations see variations 1.27 basic example: designation for tape and reel packaging lead option (optional) lf = lead free ln = lead free annealed pattern number (2 or 3 digit number for parts with rom code patterns) package type m = soic revision designator (will not correlate with datasheet revision) device type p xxxx y m ppp lx- t
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